This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-093867, filed Mar. 28, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory, and in particular, to an effective technique applied to a magnetic random access memory.
2. Description of the Related Art
Currently, as one of the next-generation nonvolatile semiconductor memory devices, a magnetic random access memory (MRAM) using a magnetic tunneling junction (MTJ) element is being developed.
The basic structure of a memory cell of the MRAM is a structure generally called a 1Tr/1MTJ structure formed from one cell selecting transistor and one MTJ element which stores data. Reading of data from the memory cell of the 1Tr/1MTJ structure is carried out by sensing the difference between the electric current flowing at an object-of-reading cell and the electric current flowing at a reference cell. (reference publication: ISSCC 2000 DIGEST OF TECHNICAL PAPERS, pp. 130-131, xe2x80x9cNonvolatile RAM Based on Magnetic Tunnel Junction Elementsxe2x80x9d M Durlam et al., Feb. 7, 8, and 9, 2000.)
FIG. 8A is a circuit diagram showing a memory cell of an MRAM having the 1Tr/1MTJ structure.
As shown in FIG. 8A, one memory cell is formed from one MTJ element 1, a cell selecting transistor 2 serially-connected to one end of the MTJ element 1, a writing word line WWL (WWL 1 in the figure) which provides an auxiliary magnetic field for writing data to the MTJ element 1, a selecting word line SWL (SWL 1 in the figure) which drives the cell selecting transistor 2, and a bit line BL serially-connected to the other end of the MTJ 1.
The bit line BL is connected to one side of a sense amplifier (S/A) 7 via a data line DL by control of a column gate 6. The gate of the column gate 6 is connected to a column selection signal line CSL. The column gate 6 selects the bit line BL in accordance with the electric potential of the column selection signal line CSL, and connects the selected bit line BL to one input of the sense amplifier 7.
The other input of the sense amplifier 7 is connected to a reference cell (REF. C) 9 via a reference cell data line DLref by control of a column gate 6xe2x80x2 for reference cell. The gate of the column gate 6xe2x80x2 for reference cell is connected to a column selection signal line CSLxe2x80x2 for reference cell. The column gate 6xe2x80x2 for reference cell connects the reference cell 9 to the other input of the sense amplifier 7 in accordance with the electric potential of the column selection signal line CSLxe2x80x2.
FIG. 9 is a sectional view showing a basic structure of the MTJ element 1.
As shown in FIG. 9, the MTJ element 1 has a structure in which an insulating layer 10 is sandwiched between two ferromagnetic layers 11, 12. Data is stored in accordance with whether the directions of magnetization of the two ferromagnetic layers 11, 12 are parallel or anti-parallel. When the directions of magnetization of the two ferromagnetic layers 11, 12 are parallel, in comparison with when the directions of magnetization are anti-parallel, the tunneling probability of the electrons-positive holes flowing at the MTJ element 1 is high. Usually, in an MRAM, a state in which the directions of magnetization of the ferromagnetic layers 11, 12 are parallel and the tunneling probability of the electrons-positive holes is high, i.e., a state in which the electrical resistance ratio is low, is defined as data xe2x80x9c1xe2x80x9d. On the other hand, a state in which the directions of magnetization of the ferromagnetic layers 11, 12 are non-parallel and the tunneling probability of the electrons-positive holes is low, i.e., a state in which the electrical resistance ratio is high, is defined as data xe2x80x9c0xe2x80x9d.
The sense amplifier 7 distinguishes whether the data is xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d by sensing the difference between the electric current flowing at the object-of-reading cell and the electric current flowing at the reference cell 9. At the time of this reading, the larger the difference between the electric currents, the faster the reading speed, and this is advantageous for making the operation high-speed.
Here, an MRAM having a 2Tr/2MTJ structure, instead of the 1Tr/1MTJ structure, has come to be developed. (reference publication: ISSCC 2000 DIGEST OF TECHNICAL PAPERS, pp. 128-129, xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cellxe2x80x9d Roy Scheuerlein et al., Feb. 7, 8, and 9, 2000.)
FIG. 10A is a circuit diagram showing a memory cell of an MRAM having the 2Tr/2MTJ structure.
As shown in FIG. 10A, in the 2Tr/2MTJ structure, by making electric current flow to a pair of bit lines BL, /BL in different directions at the time of writing, data are complementarily written such that one of two MTJ elements 1-0, 1-1 is in a state of data xe2x80x9c1xe2x80x9d and the other is in a state of data xe2x80x9c0xe2x80x9d. At this time, by making electric current flow at the writing word line WWL, a writing auxiliary magnetic field is provided to each of the MTJ elements 1-0, 1-1, and it is possible to write data selectively to only the memory cells which are the intersections of the selected bit lines BL, /BL and the writing word line WWL.
At the time of reading data, two cell selecting transistors 2-0, 2-1 are simultaneously driven, and a difference between electric currents flowing at the bit lines BL, /BL via the two MTJ elements 1-0, 1-1 is sensed by the sense amplifier 7.
In such a 2Tr/2MTJ structure, because data are complementarily written into the two MTJ elements 1-0, 1-1, the difference between the currents can be larger than in the 1Tr/1MTJ structure.
However, the amount of electric current flowing at the bit lines and the data lines via the MTJ elements depends on the channel width of the cell selecting transistor. Hereinafter, the channel width of the cell selecting transistor will be described.
FIG. 8B is a plan view showing a memory cell array in which memory cells having a 1Tr/1MTJ structure are integrated.
As shown in FIG. 8B, an element isolation region 21 is formed on a semiconductor substrate, e.g., a silicon substrate, and active areas (AA) 22 at which a source, a drain, and a channel of the cell selecting transistor 2 are formed are partitioned by the element isolation region 21. The broken lined frame CELL in FIG. 8B shows a region at which one memory cell is disposed, and the cell pitch P per one MTJ element is the sum of an element isolation width W_iso of one element isolation region 21 and a width W0 of one active area 22.
P=W0+Wxe2x80x94iso
Here, because the width W0 of the active area 22 is substantially equal to the channel width of the cell selecting transistor 2 in which the selecting word line SWL is a gate, hereinafter, in this specification, the width W0 is identified as the channel width. Therefore, the channel width W0 of the cell selecting transistor 2 in the 1Tr/1MTJ structure is:
W0=Pxe2x88x92Wxe2x80x94iso
FIG. 10B is a plan view showing a memory cell array in which memory cells having a 2Tr/2MTJ structure are integrated.
As shown in FIG. 10B, a planar pattern of the 2Tr/2MTJ structure follows the planar pattern of the 1Tr/1MTJ structure. Therefore, the channel width W0 per one cell selecting transistor is, in the same way as that of the 1Tr/1MTJ structure:
W0=Pxe2x88x92Wxe2x80x94iso
In this way, if the channel width W0 of the cell selecting transistor is limited by reducing a chip area or the like, the electric current flowing at the MTJ element at the time of reading is limited, and therefore, it is disadvantageous for high speed reading.
A semiconductor integrated circuit device according to an aspect of the present invention comprises: a plurality of magnetic tunneling junction elements; a writing word line which applies an auxiliary magnetic field for writing data to the plurality of magnetic tunneling junction elements; a plurality of bit lines connected to ones of ends of the respective plurality of magnetic tunneling junction elements; a cell selecting transistor commonly connected to other ends of the respective plurality of magnetic tunneling junction elements; and a selecting word line which drives the cell selecting transistor.